The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to electronics packaging methods and structures including redundant bond pads for non-destructive testing of integrated circuit chips.
In order to minimize the shipment of modules with defective integrated circuit chips, integrated circuit chips are subjected to tests during various stages of fabrication prior to and subsequent to dicing. It is particularly difficult and expensive to test integrated circuit chips after dicing. One reason is that an integrated circuit chip must be tested through its pins and contacts or pads before populating the carrier, card, board, or the like. The chip is then tested as part of an assembly and when complete, the chip is removed from the card or board. This is not a simple “desoldering” step, especially in the case of high input/output (I/O) density chips, encapsulation chip connect technologies, and multi-chip modules. In these instances, the chip site is redressed and a new chip installed for testing.